Energy Efficient Task Scheduling Algorithms for Performance Asymmetric Multicore Architectures

Abstract

Attaining high-performance and power efficiency has become a critical issue in modern embedded systems. To address this issue, computer architects have integrated the single-ISA heterogeneous cores on the same chip known as asymmetric multicore processors (AMPs), which also satisfies the diverse computational requirements efficiently in real-time. Despite its benefits, resource administration in terms of scheduling and mapping the tasks onto appropriate cores become a challenging task. In this paper, we targeted such AMP systems for emulation and develop an intelligent scheduling heuristic for MiBench workloads execution. The proposed semi-dynamic energyefficient scheduling algorithm (SD-EESA) comprises workload modeling, prioritization, and mapping stages. Workloads are modeled as directed acyclic graphs (DAG) with combination of nodes and edges. In the second phase, these nodes are prioritized in the non-increasing order of its cost value and allocated to active processors based on the online profiling data in terms of core utilization, which is a novel method compare to traditional models. The simulated environment shows an improvement of 30.6% and 14.6% in overall execution time and 34.9% and 19.2% in energy reduction for MiBench workloads than traditional heterogeneous earliest finish time (HEFT), Robust-HEFT.