A Review On Multiplier Architecture And Optimization

Abstract

In arithmetic operation, Multiplier plays an important role in DSP, VLSI, Microprocessor, Microcontroller, IC and SOC. Multiplier logic is observed to be an interior part to perform a numerical task. However, designing a Multiplier for any Integrated circuits or DSP application leads to power dissipation and low speed. To overcome this critical part, Different techniques are implemented to increase multiplier speed, reduce power consumption, delay, area, and computation time. This paper, review on the development of different multiplier architecture, adder, and optimize area in usage level.