Analysis of Accuracy Tradeoff Multiplier for Imprecise computing system

Abstract

Dynamic—Multiplication is a key focal limit with respect to some blunder tolerant applications. Harsh augmentation is seen as a successful methodology for trading off vitality against execution and precision. This paper proposes a 16 bit multiplier
accumulator. The proposed arrangement can effectively pick the length of the convey proliferation to satisfy the exactness essentials adaptable. The partial product tree of the multiplier is approximated by the proposed tree blower. A multiplier design is realized by using the carry maskable adder and the compressor. The Multiplier-accumulator (MAC) unit supports huge number of digital signal processing (DSP) applications.